Article ID: 000081752 Content Type: Troubleshooting Last Reviewed: 08/30/2015

RapidIO IP Core User Guide Lists Wrong TOP_LEVEL_NAME for ModelSim Simulation of Arria 10 IP Core Variations

Environment

  • Quartus® II Subscription Edition
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT

    Critical Issue

    Description

    The name of the RapidIO IP core top-level file for simulation in the ModelSim simulator changed in the IP core v14.1 and later, for simulation of IP core variations that target an Arria 10 device. The user guide lists the filename <your_ip>_altera_rapidio_140.tb_rio. However, the correct filename, starting in IP core version 14.1, is <your_ip>_altera_rapidio_<version>.tb. The RapidIO MegaCore Function User Guide is not updated with this change.

    For a similar issue with non-Arria 10 variations, refer to RapidIO Core User Guide Lists Wrong TOP_LEVEL_NAME for ModelSim Simulation of Non-Arria 10 IP Core Variations.

    Resolution

    Ensure that you simulate your Arria 10 RapidIO IP core in the ModelSim simulator with TOP_LEVEL_NAME set to <your_ip>_altera_rapidio_<version>.tb. For Arria 10 variations of the IP core, replace the simulation instruction

    set TOP_LEVEL_NAME <your_ip>_altera_rapidio_140.tb_rio

    with the new simulation instruction

    set TOP_LEVEL_NAME <your_ip>_altera_rapidio_<version>.tb

    This issue will be fixed in a future version of the RapidIO MegaCore Function User Guide.

    Related Products

    This article applies to 1 products

    Intel® Arria® 10 FPGAs and SoC FPGAs

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