Article ID: 000081751 Content Type: Error Messages Last Reviewed: 05/07/2013

Error (175020): Illegal constraint of PLL output counter to the region (X, Y) to (X, Y): no valid locations in region Error (177013): Cannot route from the PLL output counter output to destination dual-regional clock driver

Environment

BUILT IN - ARTICLE INTRO SECOND COMPONENT
Description

You may experience the below fitter error when compiling a UniPHY-based memory controller in Cyclone® V SoC and Arria® V SoC device. The error occurs because the FPGA device does not have dual-regional clocks in certain portions of the chips.

Error (175020): Illegal constraint of PLL output counter to the region (X, Y) to (X, Y): no valid locations in regionError (177013): Cannot route from the PLL output counter output to destination dual-regional clock driver because the destination is in the wrong region

Resolution

The workaround is to change pll_avl_clk, pll_config_clk, and pll_addr_cmd_clk from dual-regional clock to regional clock in the .QSF file as follows:

From:
set_instance_assignment -name GLOBAL_SIGNAL "DUAL-REGIONAL CLOCK" -to if0|pll0|pll_addr_cmd_clk
set_instance_assignment -name GLOBAL_SIGNAL "DUAL-REGIONAL CLOCK" -to if0|pll0|pll_avl_clk
set_instance_assignment -name GLOBAL_SIGNAL "DUAL-REGIONAL CLOCK" -to if0|pll0|pll_config_clk

To:
set_instance_assignment -name GLOBAL_SIGNAL "REGIONAL CLOCK" -to if0|pll0|pll_addr_cmd_clk
set_instance_assignment -name GLOBAL_SIGNAL "REGIONAL CLOCK" -to if0|pll0|pll_avl_clk
set_instance_assignment -name GLOBAL_SIGNAL "REGIONAL CLOCK" -to if0|pll0|pll_config_clk

Related Products

This article applies to 6 products

Arria® V ST SoC FPGA
Arria® V SX SoC FPGA
Cyclone® V SX SoC FPGA
Cyclone® V SE SoC FPGA
Cyclone® V FPGAs and SoC FPGAs
Cyclone® V ST SoC FPGA

Disclaimer

1

All postings and use of the content on this site are subject to Intel.com Terms of Use.