Due to a problem in the Quartus® II software you will receive the above error when simulating a VHDL instantiation of altera_mult_add Megafunction.
To workaround this problem you must modify the .vhd file for the variant you created.
First, note the bit width of datab_0, for example the following uses a 17-bit wide datab_0:
datab_0 : in std_logic_vector(16 downto 0) := (others => \'0\'); -- datab_0.datab_0
Second, modify the parameter "width_b" to match the width you found above. This parameter will appear in multiple places and you must modify all occurences:
component altera_mult_add is
generic (
number_of_multipliers : integer := 1;
width_a : integer := 16;
width_b : integer := 17;
<instance name> : component altera_mult_add
generic map (
number_of_multipliers => 1,
width_a => 16,
width_b => 17,-- Retrieval info: <generic name="width_b" value="17" />
Third, you must modify the input value of scaninb in the component declaration:
port map (
result => result, -- result.result
dataa(15 downto 0) => dataa_0(15 downto 0), -- dataa_0.dataa_0
datab(15 downto 0) => datab_0(15 downto 0), -- datab_0.datab_0
clock0 => clock0, -- clock0.clk
scaninb => "00000000000000000", -- (terminated)
This problem is fixed in Quartus-II software version 13.1