After enabling the option "Enable User Auto-refresh Controls" in the DDR2 or DDR3 SDRAM Controller with UniPHY MegaWizard you should see the following three signals added to the top level HDL file:
VHDL:
local_refresh_ack : OUT STD_LOGIC;
local_refresh_chip : IN STD_LOGIC_VECTOR (0 DOWNTO 0);
local_refresh_req : IN STD_LOGIC;
Verilog:
input local_refresh_req;
input [1 - 1: 0]local_refresh_chip;
output local_refresh_ack;
Similarly after enabling the option "Enable Self Refresh Controls" in the DDR2 or DDR3 SDRAM Controller with UniPHY MegaWizard you should see the following two signals added to the top level HDL file:
VHDL:
local_self_rfsh_ack : OUT STD_LOGIC;
local_self_rfsh_req : IN STD_LOGIC;
Verilog:
input local_self_rfsh_req;
output local_self_rfsh_ack;
Due to a problem with the generation process in the Quartus® II software versions 10.1 SP1 and earlier these ports are missing from the top level MegaWizard generated file. They are however correctly implemented in all lower level files and relevant instantiations.
To workaround this issue you should manually add these pins to the top level MegaWizard generated file.
This issue is scheduled to be resolved in a future release of the Quartus II software.
