Description
The address translation to the Avalon®-MM slave ports on the Serial RapidIO® MegaCore will be incorrect when using VHDL generation within Qsys.
Qsys always uses vectors with bounds that extend to 0, but the Serial RapidIO MegaCore specifies addresses down to 2.
Resolution
This problem does not occur when using the Verilog language within Qsys.
This problem will be fixed in a future version of the Quartus® II software.