Article ID: 000081694 Content Type: Troubleshooting Last Reviewed: 10/05/2012

What are the channel placement guidelines when using LVDS with DPA and soft-CDR mode in Stratix III, Stratix IV, Arria II HardCopy III, and HardCopy IV devices?

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    Description

    This describes the channel placement guidelines when using LVDS in DPA and Soft-CDR mode.  Table 1 below depicts the maximum LVDS channel distance from the PLL supported based on the data rate for Stratix® III, Stratix IV, Arria® II HardCopy® III, and HardCopy IV devices:

     

    Table 1. Supported Maximum LVDS channel distance from PLL based on data rate

    Data Rate Range (Gbps)Max # Full Duplex LVDS channels from PLL
    >=1.25018
    1.000 to <1.25020
    0.500 to <122
    < 0.530

    When using center PLLs to drive DPA enabled LVDS channels, the channel count in Table 1 represents channel distance in one direction.  A center PLL can drive each direction, thus the total number of DPA enabled LVDS channels that can be driven by center PLLs is 2x the number shown in Table 1.  For example, for data rates greater than or equal to 1.25Gbps, a center PLL can drive 18 channels above, and 18 channels below, for a total of 36 channels. 

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    Related Products

    This article applies to 10 products

    HardCopy™ III ASIC Devices
    Arria® II GZ FPGA
    Arria® II GX FPGA
    Stratix® IV GT FPGA
    Stratix® IV E FPGA
    Stratix® IV GX FPGA
    HardCopy™ IV GX ASIC Devices
    HardCopy™ IV E ASIC Devices
    Stratix® IV FPGAs
    Stratix® III FPGAs

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