Article ID: 000081691 Content Type: Troubleshooting Last Reviewed: 09/11/2012

When I simulate dynamic channel reconfiguration in Stratix II GX devices, why does the rx_freqlocked go low for all transceiver channels that are connected to the reconfig controller?

Environment

BUILT IN - ARTICLE INTRO SECOND COMPONENT
Description

In Stratix® II GX simulation, consider a case where you use multiple transceiver channels in your design driven by a single dynamic reconfig controller. During the first time when you perform channel reconfiguration on a transceiver channel, the rx_freqlocked and rx_clkout of all channels that are connected to the reconfig controller goes to zero for a few clock cycles. This occurs because the receive PLLs in the simulation model requires a relock when channel reconfiguration is enabled. This issue happens only in simulation during the first time you initiate channel reconfiguration. To work around this issue, perform the following one-time write sequence as part of your system initialization when you assert 'gxb_powerdown' or 'rx_analogreset' signals.

The signals that are referred in the write sequence below correspond to the input and output ports of the ALT2GXB_RECONFIG instantiation in your design.

1. Set the 'reconfig_mode_sel' signal to '001. Write the default .hex/.mif file contents for two 'reconfig_address_out' signal increments. That is, pulse the 'write_all' signal for the 'reconfig_address_out' 0 and 1 based on the 'busy' and 'reconfig_address_en' signals.

2. The .hex/.mif file selected for writing should correspond to the default configuration in the ALT2GXB Megawizard® Plug-in Manager. For example, if you have two .hex/.mif files that correspond to GIGE and SONET OC48 protocols, and if you have set GIGE  as your default configuration(the protocol set in the 'General' screen of the ALT2GXB Megawizard), then write the the first two words of the .hex/.mif file generated for GIGE protocol.

3. After you complete writing the first two words, wait for the 'busy' signal to go low and assert the 'reset_reconfig_address' signal to initialize the 'reconfig_address_out' to zero.

 

 

 

Related Products

This article applies to 1 products

Stratix® II GX FPGA

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