Error (10528): VHDL error at <filename.vhd>(): value "0" is outside the target constraint range (1 to 2147483647)

Due to a problem in the Quartus® II software version 13.0 and earlier, designs using Qsys with Avalon-ST adapters may encounter the above error during synthesis. This problem affects Qsys systems generated in VHDL. The problem does not affect Qsys systems generated in Verilog HDL. This problem is due to incorrect data types in <Quartus II installation directory>/ip/altera/avalon_st/altera_avalon_st_adapter/altera_avalon_st_adapter_hw.tcl.

To work around this problem, download the file below to <Quartus II installation directory>/ip/altera/avalon_st/altera_avalon_st_adapter.

• altera_avalon_st_adapter_hw.tcl

After updating the file, referesh the system and regenerate the system for VHDL synthesis files.

This problem is fixed beginning with the Quartus II software version 13.0 SP1.