Article ID: 000081679 Content Type: Troubleshooting Last Reviewed: 08/25/2015

Why can't I place a DDR3 UniPHY-based controller in quadrant 1 or 2 in a Cyclone™ V or Arria™ V SoC device?


  • Quartus® II Subscription Edition
  • PLL
  • Clock

    If you try to place a DDR3 UniPHY-based controller in quadrant 1 or 2, you will get the following errors.

    Error (175020): Illegal constraint of PLL output counter to the region (0, 31) to (0, 81): no valid locations in region
    Error (177013): Cannot route from the PLL output counter output to destination dual-regional clock driver because the destination is in the wrong region

    UniPHY-based controllers use dual-regional clocks for the pll_afi_clk, pll_addr_cmd_clk and pll_config_clk signals. This is to allow an interface to span an entire side of a device.

    Certain quadrants of Cyclone V SoC and Arria V SoC devices do not have dual-regional clocks. 


    Placing a DDR3 UniPHY-based controller in quadrant 1 or 2 is possible. You must ensure that in the QSF file the DDR3 controller uses regional clock assignments, instead of dual-regional clock assignments.

    Related Products

    This article applies to 7 products

    Cyclone® V FPGAs and SoC FPGAs
    Arria® V FPGAs and SoC FPGAs
    Cyclone® V SE SoC FPGA
    Arria® V ST SoC FPGA
    Arria® V SX SoC FPGA
    Cyclone® V ST SoC FPGA
    Cyclone® V SX SoC FPGA



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