Article ID: 000081678 Content Type: Troubleshooting Last Reviewed: 08/13/2012

TSE SGMII bridge causes Ref_Clk source placement Error.

Environment

  • Cyclone® IV GX FPGA
  • Ethernet
  • PLL
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    Enabling the SGMII bridge in the TSE IP results in the rate-adaptation logic being implemented in the FPGA fabric (not in the Transceiver). This means that the Ref_Clk signal must be able to connect directly to the GCLK network.

    In Cyclone® IV devices REFCLK[0,1] and REFCLK[4,5] cannot connect directly to the GCLK network, hence the no fit error - Error (176559):  Can't place MPLL or GPLL PLL.

    Resolution In Cyclone IV GX devices, REFCLK[0,1] and REFCLK[4,5] cannot connect directly to the GCLK network, hence if the SGMII bridge is enabled, Ref_Clk must be connected to an alternative dedicated clock input pin.

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