Article ID: 000081618 Content Type: Troubleshooting Last Reviewed: 08/15/2012

Why does my Shift Register (RAM-based) megafunction fail in gate-level simulation and hardware verification?

Environment

  • Quartus® II Subscription Edition
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    Due to a problem in the Quartus® II software version 10.1 SP1 and earlier, the Shift Register (RAM-based) MegaWizard™ Plug-In allows you to use the clken port on the megafunction when MLAB is selected as the memory block type. MLAB memory blocks are not suitable for implementing shift registers using the clken port. This may result in failures during gate-level simulation or hardware verification of the shift register.

    To work around this problem, select other memory block types when implementing a Shift Register (RAM-based) megafunction using the clken port.

    The clken port is disabled when MLAB is selected as the memory block type in the Shift Register (RAM-based) wizard beginning with the Quartus II software version 11.0.

    Related Products

    This article applies to 5 products

    Stratix® III FPGAs
    Arria® II GX FPGA
    Stratix® IV E FPGA
    Stratix® IV GX FPGA
    Stratix® IV GT FPGA

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