The FPGA normally pulls the nSTATUS pin low when an error occurs during configuration. At the beginning of configuration, the FPGA needs to receive a preamble pattern in the configuration data (the preamble pattern for a configuration file is included automatically when the Quartus® II software generates the configuration file). If the FPGA does not receive this preamble pattern correctly, the FPGA will not be able to recognize a configuration error even after the entire configuration data has been sent to the FPGA. This results in the nSTATUS signal remaining high and the CONF_DONE signal remaining low.
If you see this symptom, check your setup to ensure that the FPGA is able to receive the configuration data correctly based on your programming files.