Article ID: 000081585 Content Type: Troubleshooting Last Reviewed: 09/26/2013

Can I connect the xgmii_rx_clk or xgmii_tx_clk ports to the rx_coreclkin port of the 10GBASE-R PHY IP?

Environment

  • Stratix® V GX FPGA
  • Stratix® V GS FPGA
  • Stratix® V GT FPGA
  • Arria® V GT FPGA
  • Arria® V GX FPGA
  • Arria® V GZ FPGA
  • Arria® V ST SoC FPGA
  • Arria® V SX SoC FPGA
BUILT IN - ARTICLE INTRO SECOND COMPONENT
Description

No, you cannot connect the xgmii_rx_clk or xgmii_tx_clk ports to the rx_coreclkin port of the 10GBASE-R PHY IP.

Resolution

If you enable the rx_coreclkin port of the 10GBASE-R PHY IP, the 156.25 MHz rx_coreclkin signal must be generated outside of the IP.

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