Article ID: 000081579 Content Type: Troubleshooting Last Reviewed: 01/09/2012

Definition of fixedclk Incorrect for PHY IP Core for PCI Express (PIPE)

Environment

  • Quartus® II Subscription Edition
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT

    Critical Issue

    Description

    The definition of fixclk in version 11.1 in the PHY IP Core for PCI Express (PIPE) chapter of the Transceiver PHY IP Core User Guide, states that it must be connected to a separate, free running clock input source. However, this separate clock is unnecessary. You can derive fixedclk from pll_ref_clk.

    Resolution

    No workaround is necessary. This issue is fixed in version 12.0 of the Transceiver PHY IP Core User Guide.

    Related Products

    This article applies to 1 products

    Stratix® V FPGAs

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