Critical Issue
Description
The definition of fixclk in version 11.1 in the PHY
IP Core for PCI Express (PIPE) chapter of the Transceiver
PHY IP Core User Guide, states that it must be connected
to a separate, free running clock input source. However, this separate
clock is unnecessary. You can derive fixedclk from pll_ref_clk.
Resolution
No workaround is necessary. This issue is fixed in version 12.0 of the Transceiver PHY IP Core User Guide.