Yes, due to a problem with the Quartus® Prime software version 16.0 and earlier, reconfiguration of C counters in IOPLLs may not work correctly. The issue happens because the logical to physical counter mapping is not generated correctly in some compilations. This causes the intended C counter not to be reconfigured correctly when performing a reconfiguration in user mode.
To work around this problem, you can manually re-order the IOPLL output counters used in the design. Follow the steps below to re-order the output counters:
Put the following line into a quartus.ini file and place the file in the project directory:
cpll_disable_oport_rotation=on- Determine the physical output counters used in a compilation.
Use the Read_PLL_Setting.tcl to read out the physical C counter settings used in the design. Refer to the README section in the tcl file for instructions on how to use the script.
Download Read_PLL_Setting.tcl file
- Cross reference to PLL Summary Report to identify the physical counter used.
- Regenerate the IOPLL IP to re-order the output clock based on physical counter identified in step 2. This is not required on IOPLL used for external memory interface.
EXAMPLE:
Consider the following IOPLL IP and the physical counters used in a compilation
| Output Clock in IOPLL IP | Frequency | Physical Counter |
| Outclk0 | A | C4 |
| Outclk1 | B | C5 |
Regenerate the IOPLL IP with the following parameters
| Output Clock in IOPLL IP | Frequency |
| Outclk0 | Don't Care (either A or B) |
| Outclk1 | Don't Care (either A or B) |
| Outclk2 | Don't Care (either A or B) |
| Outclk3 | Don't Care (either A or B) |
| Outclk4 | A |
| Outclk5 | B |
- Constrain the IOPLL location based on a passing compilation.
- Make the necessary connection changes in the RTL files.
- Update the SDC file with the re-ordered clock name (if applicable).
- Recompile the design.
This issue will be fixed in future release of the Quartus Prime software.