Article ID: 000081574 Content Type: Product Information & Documentation Last Reviewed: 02/25/2013

How should I set the termination settings when I require HCSL standard on the transceiver REFCLK pin for PCI Express Protocol?

Environment

  • Quartus® II Subscription Edition
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    The Quartus® II software version 9.1 incorrectly enables internal termination if you set the HCSL IO standard on the transceiver REFCLK pins for Stratix® IV and Arria® II GX devices. You can select this IO standard option only if the transceiver is configured in PCI Express (PIPE) functional mode. 

    Resolution

    To work around this problem, follow the steps below and use DC coupling with external termination on the clock pin.

    1. Add the following assignment to your project .qsf file
      set_instance_assignment -name INPUT_TERMINATION OFF -to <refclk_pin_name>
    2. Re-compile the design

    This problem is fixed beginning with the Quartus II software version 9.1 SP1.

    Related Products

    This article applies to 4 products

    Arria® II FPGAs
    Stratix® IV GX FPGA
    Arria® II GX FPGA
    Stratix® IV FPGAs

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