Article ID: 000081556 Content Type: Error Messages Last Reviewed: 07/28/2015

Error: domain_0_default_slave: altera_error_response_slave does not support generation for VHDL Simulation

Environment

    Quartus® II Subscription Edition
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Description

Due to a problem with the Quartus® II software version 15.0 (windows only), Qsys systems that include the altera_error_response_slave IP, fails to generate VHDL simulation models and testbenches.

Resolution

 

To workaround this problem Verilog should be used for Simulation.

This problem will be fixed in future version of the QuartusII software.

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This article applies to 1 products

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