Critical Issue
Description
When you compile the 10GbE MAC with 10GBASE-R PHY design example in Stratix V devices, the Quartus II TimeQuest Timing Analyzer reports a failure in the Clock Setup timing analysis report. It may also report a failure in the Clock Hold timing analysis report.
This issue affects the 10GbE MAC with 10GBASE-R PHY design example in Stratix V devices.
Resolution
To avoid this issue, follow these steps before compiling the design example:
- Open the SDC constraint file top.sdc in the altera_eth_10g_mac_base_r directory.
- Add the following line to the file:
set_clock_groups -exclusive -group {clk_50Mhz} -group {*|ch[0].sv_xcvr_10gbaser_native_inst|tx_pll|altera_pll_156M~PLL_OUTPUT_COUNTER|divclk}
This issue will be fixed in a future version of the 10-Gbps Ethernet MAC MegaCore function.