Critical Issue
Description
When trying to access SDRAM through the SoC’s FPGA-to-SDRAM interface, your design might experience a bus failure, resulting in either of the following symptoms:
- The FPGA-to-SDRAM interface hangs
- The interface transfers spurious data
Resolution
If your design uses the FPGA-to-SDRAM interface, you must download and install a software patch. If you are using Quartus II v12.1, you must first upgrade to v13.0.
Download and install the latest Stratix V/Arria V/Cyclone V device patch from the Altera Knowledge Base, at http://www.altera.com/support/kdb/solutions/rd05172013_891.html.