Article ID: 000081503 Content Type: Troubleshooting Last Reviewed: 03/26/2015

Why are some pins of adjacent banks placed on different edges of the package?

Environment

BUILT IN - ARTICLE INTRO SECOND COMPONENT
Description

Due to the physical packaging requirements, you may see pins from adjacent banks on different edges of the package. The I/O banks are adjacent and adhere to the design rules of adjacent banks.

 

Related Products

This article applies to 3 products

Intel® Arria® 10 GT FPGA
Intel® Arria® 10 GX FPGA
Intel® Arria® 10 SX SoC FPGA

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