Article ID: 000081497 Content Type: Troubleshooting Last Reviewed: 09/25/2013

What is the mapping between the Handbook defined Device Quadrants and the Quartus II Software Chip Planner Regional Clock Regions for Stratix V devices?

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Description

The mapping between the Handbook defined Device Quadrants and the Quartus® II Software Chip Planner Regional Clock Regions for Stratix® V devices is as follows:

Device Quadrant 1 = Regional Clock Region 0
Device Quadrant 2 = Regional Clock Region 1
Device Quadrant 3 = Regional Clock Region 3
Device Quadrant 4 = Regional Clock Region 2

Resolution This information will be added to a future version of the Stratix V Handbook.

Related Products

This article applies to 4 products

Stratix® V E FPGA
Stratix® V GS FPGA
Stratix® V GT FPGA
Stratix® V GX FPGA

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