Article ID: 000081492 Content Type: Troubleshooting Last Reviewed: 05/12/2014

RapidIO II IP Core Incorrectly Sets Illegal Transaction Decode Flag Instead of Unsupported Transaction Flag

Environment

    Quartus® II Subscription Edition
BUILT IN - ARTICLE INTRO SECOND COMPONENT

Critical Issue

Description

In response to an incoming RapidIO read transaction with rdsize greater than 4’b1011 and address[0] set to 1, the RapidIO II IP core should set the Unsupported Transaction (UNSUPPORT_TRAN) bit in the Logical/Transport Layer Error Detect CSR (offset 0x308) and return an ERROR response.

However, under these circumstances the RapidIO II IP core sets the Illegal Transaction Decode (ILL_TRAN_DECODE) bit in the register and does not set the UNSUPPORT_TRAN bit.

Resolution

This issue has no workaround.

This issue will be fixed in a future version of the RapidIO II MegaCore function.

Related Products

This article applies to 1 products

Intel® Programmable Devices

1

Need more help?

Contact support

Disclaimer

1

All postings and use of the content on this site are subject to Intel.com Terms of Use.