In Interlaken PHY IP Core, the Quartus II software reports Minimum Pulse Width violations for some PHY clock signals

In Interlaken PHY IP Core, the Quartus II software reports minimum pulse width violations for Interlaken PHY design on the following clock signals:

altera_pcs|ilkn_pcs_10gbps_inst|sv_ilk_inst|bonded_lane_inst|inst_sv_xcvr_native[0].interlaken_inst|inst_sv_pma|rx_pma.sv_rx_pma_inst|rx_pmas[0].rx_pma.rx_pma_deser|clk90b

altera_pcs|ilkn_pcs_10gbps_inst|sv_ilk_inst|bonded_lane_inst|inst_sv_xcvr_native[0].interlaken_inst|inst_sv_pma|tx_pma.sv_tx_pma_inst|tx_pma_insts[0].sv_tx_pma_ch_inst|tx_pma_ch.tx_cgb|pclk[1]

These minimum pulse width violations are for false paths. Please ignore these paths. This issue has been fixed in Quartus II v12.0SP2 for Stratix V production device.