Article ID: 000081471 Content Type: Error Messages Last Reviewed: 03/04/2013

Internal Error: Sub-system: TIS_RC, File: /quartus/tsm/tis/tis_physical_timing_av_ffpll.cpp, Line: 584

Environment

  • Quartus® II Subscription Edition
  • PLL
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description Due to a problem in the Quartus® II software version 12.0 and later, you may see this error during the Fitter if your design targets a Stratix® V desgin containing an Altera_PLL with an output clock that is unconnected.
    Resolution

    To work around this problem, either connect the PLL output clock to your desired logic or remove it from the instantiation of the Altera_PLL.

    This problem is scheduled to be fixed in a future release of the Quartus II software.

    Related Products

    This article applies to 4 products

    Stratix® V GX FPGA
    Stratix® V GT FPGA
    Stratix® V GS FPGA
    Stratix® V E FPGA

    Disclaimer

    1

    All postings and use of the content on this site are subject to Intel.com Terms of Use.