Article ID: 000081464 Content Type: Troubleshooting Last Reviewed: 09/02/2012

Why do I see mem_k and mem_k_n clock pair as unconstrained output ports in TimeQuest when I implement QDRII SRAM UniPHY based controller?

Environment

BUILT IN - ARTICLE INTRO SECOND COMPONENT
Description

Quartus® II software and IP version 10.0 reports mem_k and mem_k_n clock pair as unconstrained output ports because the SDC file generated by the megawizard is missing set_false_path constraint for the clock pair.

Add follwing constraint in the SDC file to fix the issue:

foreach { pin } [concat ] {

                                set_false_path -to [get_ports ]

                }

 

This issue will be fixed in the next version of the Quartus II software and the IP.

Related Products

This article applies to 4 products

Stratix® III FPGAs
Stratix® IV GT FPGA
Stratix® IV GX FPGA
Stratix® IV E FPGA

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