Article ID: 000081447 Content Type: Troubleshooting Last Reviewed: 09/05/2012

Why are the PCI input timing requirements in my Stratix® or Stratix GX design not being met?



With PCI Compiler 3.2.0 and Quartus® II 4.1, you may occasionally see PCI designs failing to meet the input timing requirements when targeting Stratix or Stratix GX devices. For a 66 MHz PCI operation, the PCI input signals need to meet an input setup requirement (tsu) of 3 ns and a hold requirement (th) of 0 ns. For a 33 MHz PCI operation, the PCI input signals need to meet tsu requirement of 7 ns and th requirement of 0 ns. The input setup failures affect designs requiring 66 MHz operation only. The hold failures can affect designs requiring either 66 MHz operation or 33 MHz operation. The failure happens when there is a PCI input signals (like trdyn) controlling a PCI output register (like AD) going through two levels of logic (two LEs). To get the maximum slack on tsu Quartus II must place both the LEs in a Logic Array Block (LAB) near to the output register. Quartus II places the logic at the right location 99% of the times (this analysis is with the core by itself). The 1% failure is purely random. Typically you would see 1 or 2 paths failing to meet the tsu requirement. The failure margin for tsu is typically in the range of 50 ps to 500 ps. For th failures you could see several paths failing to meet the requirements.

In order to meet timing, perform the following steps:

  1. Use an Altera® provided constraint file

    Make sure that you are using an Altera provided constraint file correctly. For more information, please refer to Appendix B of the PCI Compiler User Guide rev. 3.2.0.

  2. Change the Quartus II Fitter seed

    Changing the fitter seed will typically resolve most of the timing failures and is the recommended solution for resolving input timing failures. Changing the seed affects the initial placement configuration and often causes different fitter results. The Quartus II Fitter uses the seed as the initial placement configuration when attempting to optimize the design's timing requirements. Because each seed value will result in a somewhat different fit, you can try several seeds to attempt to obtain superior fitting results. The seed for initial placement is controlled by the Seed setting on the Fitter Settings page of the Settings dialog box (Assignments menu). By default, the Quartus II Fitter uses a seed of 1. You can specify any other non-negative integer value as the seed. For more information on changing the seed, please refer to the Quartus II handbook or Quartus II online help.

    Changing the seed may or may not produce better fitting; therefore, you may need to try different seeds so you can achieve a better fit. Once the design meets timing, you can lock the seed. However, any change to the design after the seed has been locked may result in failures again. You can also use the Altera Design Space Explorer (DSE) to sweep complex flow parameters, including the seed, in the Quartus II software to optimize design performance. For more information about DSE, refer to Quartus II handbook or Quartus II online help. The rest of the document provides some other options that the user can try to resolve the input timing failures. Altera recommends that these options be tried only when changing the seed does not solve the problem.

  3. Specify tighter tsu requirements

    For tsu failures, you can specify a tighter tsu requirement on the failing PCI input. For instance, if the failing tsu path originates from the PCI signal trdyn then change the tsu requirement for this signal to 2.9 ns instead of 3.0 ns. The tsu requirement can be changed by selecting the Timing Category in the Assignment Editor Page (Assignments menu) and modifying the tsu requirement for the trdyn signal.

  4. Increase Input Delay to meet the timing requirements

    The Stratix device IOE includes programmable delays that can be activated to ensure zero hold times. For more information on the programmable delays, please refer to the Stratix Handbook. By default, Quartus II does not include any input delays. The Quartus II logic option for increasing the input delay is called “Decrease input delay to internal cells” and its value must be set to “large”. This assignment can be made using the Assignment editor and selecting the Logic Options category. This logic assignment needs to be specified from a PCI input signal to an internal register inside the core. Alternately this logic option assignment can be made directly inside the .QSF file. The following example shows this assignment made from the PCI input signal irdyn to an internal register inside the pci_mt32 core.

    set_instance_assignment -name STRATIX_DECREASE_INPUT_DELAY_TO_INTERNAL_CELLS 
       LARGE -from irdyn -to "pci_mt32:pci_mt32_inst\|pcimt32_t:trg\|LR_PXFR_r1"

  5. Use LogicLock™ for tsu failures

    The use of LogicLock is recommended for experienced users only, as the procedure can be complicated. As explained previously the tsu failure happens when there is a PCI input signal (like trdyn) controlling a PCI output register (like AD) going through two levels of logic (two LEs). To meet timing, you can create a fixed LogicLock region and place the 2 LEs in a LAB near the output register. For more information on using LogicLock, please refer to Quartus II documentation.

  6. Use LogicLock for th failures

    In order to meet the th requirement, the user can create a LogicLock region to move the input register away from the input pin.

Related Products

This article applies to 2 products

Stratix® FPGAs
Stratix® GX FPGA



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