Article ID: 000081433 Content Type: Troubleshooting Last Reviewed: 11/16/2011

Designs Targeting Stratix V Fail to Generate Simulation Model

Environment

  • Quartus® II Subscription Edition
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT

    Critical Issue

    Description

    Designs that use the SDI MegaCore function targeting a Stratix V device fail to generate a simulation model in MegaWizard Plug-In Manager.

    Resolution

    To generate a simulation model for your Stratix V design, follow these steps:

    1. In the Quartus II software, create a project and launch the MegaWizard Plug-In Manager
    2. Create a new custom megafunction variation, and select the desired SDI configuration
    3. On the EDA tab, make sure to turn off Generate simulation model
    4. Click OK
    5. In a command terminal, change the directory to the project folder to generate xcvr and sdi-library folders
    6. Run the quartus_map script as follows:

    Verilog Example: quartus_map <proj_name>.v --simgen --simgen_parameter="CBX_HDL_LANGUAGE=Verilog" --family="Stratix V" VHDL Example: quartus_map <proj_name>.vhd --simgen --simgen_parameter="CBX_HDL_LANGUAGE=Vhdl" --family="Stratix V"The <proj_name>.vo or vho file gets generated at the project directory.

    Related Products

    This article applies to 1 products

    Stratix® V FPGAs

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