Why does my Intel® Arria® 10, 10G Multi-Rate Ethernet PHY - Lineside IP fail timing between the MAC and PHY on the TX datapath?

When using the Intel® Arria® 10, 10G Multi-rate Ethernet PHY  - Lineside IP core, you may see hold timing violations for the data transfer from alt_mge16_phy_xcvr_term module to the Native PHY transceiver on the TX data path.

To work around this issue, over-constrain the failing path by adding the following timing constraints into user's top level Synopsis Design Constraint(.sdc) file.

if { [string equal "quartus_fit" $::TimeQuestInfo(nameofexecutable)] } {
    set_min_delay -from [get_registers *alt_mge16_phy_xcvr_term:*|*] -to [get_registers *twentynm_xcvr_native:*|twentynm_pcs_*] 0.3ns
}