Article ID: 000081395 Content Type: Troubleshooting Last Reviewed: 10/14/2015

Why does my Arria 10, 10G Multi-Rate Ethernet PHY - Lineside IP fail timing between the MAC and PHY on the TX datapath?

Environment

  • Quartus® II Subscription Edition
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT

    Critical Issue

    Description When using the Arria® 10, 10G Multi-rate Ethernet PHY  - Lineside IP core you may see hold timing violations for the data transfer from alt_mge16_phy_xcvr_term module to the Native PHY transceiver on the TX data path.
    Resolution

    To work around this issue, over-constrain the failing path by adding following timing constraints into user top level Synopsis Design Constraint(.sdc) file.

    if { [string equal "quartus_fit" $::TimeQuestInfo(nameofexecutable)] } {
        set_min_delay -from [get_registers *alt_mge16_phy_xcvr_term:*|*] -to [get_registers *twentynm_xcvr_native:*|twentynm_pcs_*] 0.3ns
    }

    This issue will be fixed in a future release of the Quartus® II software. 

    Related Products

    This article applies to 3 products

    Intel® Arria® 10 GT FPGA
    Intel® Arria® 10 GX FPGA
    Intel® Arria® 10 SX SoC FPGA

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