Article ID: 000081389 Content Type: Troubleshooting Last Reviewed: 09/11/2012

Why does CMU PLL loose lock in bonded configuration before busy signal is de-asserted in Arria II GX/GZ, Stratix IV GX/GT and Hardcopy GX devices?

Environment

BUILT IN - ARTICLE INTRO SECOND COMPONENT
Description

You may see CMU PLL loose lock in bonded configuration before busy signal is de-asserted in Arria® II GX/GZ, Stratix® IV GX/GT and Hardcopy® GX devices if CMU PLL is powered down before ALTGX_RECONFIG busy signal is de-asserted during offset cancellation process. CMU PLL is powered down for internal voltage calibration in bonded configuration.

Users who use only rising edge of pll_locked signal to trigger tx_digitalreset will be affected.

The workaround is to wait for ALTGX_RECONFIG busy signal to de-assert before monitoring pll_locked.

Related Products

This article applies to 5 products

Arria® II GX FPGA
Arria® II GZ FPGA
Stratix® IV GT FPGA
HardCopy™ IV GX ASIC Devices
Stratix® IV GX FPGA

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