Article ID: 000081369 Content Type: Product Information & Documentation Last Reviewed: 02/13/2006

How long does it take to update or reconfigure the Stratix™ devices' enhanced phase-locked loops (PLLs) in real-time?

Environment

  • PLL
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description The SCANCLK port of the PLLs, which is used to shift in counter and delay element settings, can be clocked up to 25 MHz. After all the scan registers are loaded, the Stratix PLL will update to new settings and relock within 20 ms.

    Related Products

    This article applies to 1 products

    Stratix® FPGAs

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