Article ID: 000081368 Content Type: Troubleshooting Last Reviewed: 09/11/2012

Is the VCCPD voltage for Stratix III devices incorrectly reported for 3.3V I/O banks in the Quartus II software?

Environment

BUILT IN - ARTICLE INTRO SECOND COMPONENT
Description

Yes, for Stratix® III devices, the Quartus® II design software versions 7.2 SP1 and earlier incorrectly report the VCCPD voltage in the Pin-Out file (.pin) as 2.5 V for any I/O bank with the VCCIO set to 3.3V.   

If the VCCIO of an I/O bank is set to 3.3 V, the VCCPD requirement is 3.3 V. If the VCCIO of an I/O bank is set to 3.0 V, the VCCPD requirement is 3.0 V. If the VCCIO of an I/O bank is 2.5V or lower, the VCCPD requirement is 2.5V.

This problem is fixed beginning with the Quartus II software version 7.2 SP2.

Related Products

This article applies to 1 products

Stratix® III FPGAs

Disclaimer

1

All postings and use of the content on this site are subject to Intel.com Terms of Use.