Article ID: 000081367 Content Type: Troubleshooting Last Reviewed: 05/19/2014

Why is it not possible to drive out on pins that are reserved as bi-directional when performing post-configuration mode boundary scan testing on Arria V or Cyclone V devices?

Environment

  • Quartus® II Subscription Edition
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    Due to a problem in the Quartus® II software version 13.1, the output buffers of pins that are reserved as bidirectional are disabled in Arria® V or Cyclone® V devices. This may result in not being able to drive a logic \'0\' or ‘1’ when performing EXTEST during post-configuration mode boundary scan testing.

     

    Resolution

    A patch is available below to fix this problem for the Quartus® II software version 13.1. 

     

    Download the Quartus II software version 13.1a10 Patch 0.02a for Windows (.exe)

    Download the Quartus II software version 13.1a10 Patch 0.02a for Linux (.run)

    Readme for the Quartus II software version 13.1a10 Patch 0.02a (.txt)

     

    This problem is scheduled to be fixed in a future version of the Quartus II software.

    Related Products

    This article applies to 3 products

    Arria® V GT FPGA
    Arria® V GX FPGA
    Arria® V ST SoC FPGA

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