Due to a problem in the Quartus® II software version 13.0 SP1 and earlier, the power up values of RAM inferred from raw logic may be incorrect.
This problem is specific to cases where the memory is coded using a non-recommended HDL coding style.
For a list of recommended RTL memory templates, open a VHDL/Verilog HDL file in the Quartus II software and then right click and select Insert Template.
A list of RAM and ROM templates can be found under VHDL/Verilog HDL > Full Designs > Rams and ROMs.
To work around this problem, perform one of the following actions:
- Infer the RAM using the VHDL/Verilog HDL template
- Instantiate the RAM with a Memory Initialization File (.mif)
The Quartus II software version 13.1 implements the RAM bits with non-zero power values as registers.
In a future version of the Quartus II software, the power up values of RAM inferred from raw logic are scheduled to be implemented as a .mif.