Article ID: 000081356 Content Type: Troubleshooting Last Reviewed: 11/11/2011

Simulation of 10GBASE-R, Custom, Interlaken, Low Latency, PCI Express PIPE, and XAUI Transceiver PHY IP Cores Fails for Stratix V if You Use ModelSim With Mixed Languages

Environment

  • Quartus® II Subscription Edition
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT

    Critical Issue

    Description

    Simulation of 10GBASE-R, Custom, Interlaken, Low Latency, PCI Express PIPE, and XAUI Transceiver PHY IP cores for Stratix V devices fails if you use ModelSim with mixed languages.

    Resolution

    Turn off ModelSim optimization with the -novpt option of the vsim command..

    Related Products

    This article applies to 1 products

    Stratix® V FPGAs

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