Article ID: 000081344 Content Type: Troubleshooting Last Reviewed: 09/11/2012

Why do I get two chip selects when I generate a UniPHY DDR3 registered DIMM single rank configuration?

Environment

BUILT IN - ARTICLE INTRO SECOND COMPONENT
Description

Registered DIMMs contain a register for the memory address, command, and clock signals. This register has to be programmed with control words during initialization and this occurs when both chip select 0 and 1 are active low. Typically, there are sixteen control word accesses.

After the register has been initialized, the RDIMM memory is then accessed using chip select 0. Chip select 1 is only used during register initialization.

To observe this, it is recommended to run the simulation of the example design of a single rank DDR3 registered DIMM configuration and look at the signal waveforms.

Resolution

Related Products

This article applies to 3 products

Stratix® IV GX FPGA
Stratix® V GX FPGA
Stratix® III FPGAs

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