Article ID: 000081303 Content Type: Troubleshooting Last Reviewed: 09/11/2012

Why are there negative timing margins on the clock to strobe (DQS vs. CK) timing path for a design that includes the DDR2 SDRAM High Performance Controller MegaCore or ALTMEMPHY megafunction?

Environment

BUILT IN - ARTICLE INTRO SECOND COMPONENT
Description

For Stratix® II designs implementing the DDR2 SDRAM High Performance Controller MegaCore® or the ALTMEMPHY megafunction that use dedicated PLL outputs to drive external memory clock input pins, the Quartus® II software may report negative timing margins for the clock to strobe (DQS vs. CK) timing relationship. The function uses PLL outputs when the Use dedicated PLL outputs to drive memory clocks option in enabled on the PHY Settings page of the MegaWizard® Plug-In Manager.

The external memory device requires that the CK/CK# and DQS signals arrive at the same time within /- tDQSS. The ALTMEMPHY megafunction timing scripts check that these requirements are met. When you use dedicated PLL outputs to generate the memory clocks, the tCO delays on the CK/CK# output pins may be smaller than the DQS strobe output delays. This delay difference could result in timing violations for the DQS vs. CK timing relationship.

You may be able to fix these timing violations by adjusting the phase shift setting on the PLL output used to drive CK/CK# outputs. In Stratix II ALTMEMPHY designs, the c3 output counter on the PLL generates the CK/CK# outputs. The following procedure describes the steps required.

  1. Calculate the average of the setup and hold time slacks reported for the DQS vs. CK timing relationship.
  2. Determine the additional PLL phase shift required to balance the setup and hold time slacks.
  3. Use the MegaWizard Plug-In Manager to edit the ALTPLL Megafunction instance <variation_name>_phy_alt_mem_phy_pll_sii.
  4. Adjust the phase shift setting for the appropriate PLL counter output based on your results from step 2.
  5. Regenerate the PLL megafunction instance.
  6. Recompile the design and verify all timing slacks are positive.

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