Article ID: 000081272 Content Type: Troubleshooting Last Reviewed: 08/21/2023

Why does the CPL_ERR signal not toggle the appropriate error status bits in the Configuration Space registers?

Environment

    Quartus® II Subscription Edition
    Avalon-MM Arria® V Hard IP for PCI Express Intel® FPGA IP
BUILT IN - ARTICLE INTRO SECOND COMPONENT
Description

Due to a problem with the Altera® Hard IP for PCI Express® in Arria® V and Cyclone® V devices, toggling the cpl_err signal will not log the error in the Error Status registers. This issue affects all cpl_err[*] signals, but does not affect the cpl_err_func signals.

 

 

Resolution

Application Layer logic must perform an LMI write to the appropriate error register, and create the appropriate TLP, to workaround the issue described. See Table 2-29 Completion Status Field Values, in the PCI Express Base 3.0 Specification.

This problem is not scheduled to be fixed in a future Quartus® II software release.

Related Products

This article applies to 7 products

Cyclone® V GT FPGA
Arria® V GT FPGA
Cyclone® V ST SoC FPGA
Arria® V ST SoC FPGA
Cyclone® V GX FPGA
Arria® V GX FPGA
Cyclone® V SE SoC FPGA

1

Need more help?

Contact support

Disclaimer

1

All postings and use of the content on this site are subject to Intel.com Terms of Use.