Article ID: 000081264 Content Type: Product Information & Documentation Last Reviewed: 12/18/2012

How do I use an FPLL as a Tx PLL in Arria V GX and Stratix V GX devices?

Environment

  • Quartus® II Subscription Edition
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    Description

    To use an fPLL as a Tx PLL in Arria® V GX and Stratix® V GX devices, you must use the Native PHY. You should select "External PLL" mode in the Native PHY MegaWizard™ and connect the output clock of your fPLL to the ext_pll_clk input port of the Native PHY.

    Resolution

     

    Related Products

    This article applies to 2 products

    Stratix® V GX FPGA
    Arria® V GX FPGA

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