Article ID: 000081250 Content Type: Troubleshooting Last Reviewed: 11/18/2014

Why does the “Show PCIe Hard Interface Pins” option in the pin planner for the Cyclone V GX (5CGXFC5C6U19A7) device variant highlight PIN R16 (nPERST0) for a PCIe Hard IP located in the bottom transceiver bank?

Environment

  • Quartus® II Subscription Edition
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    Due to a problem in the Quartus® II software version 13.1 update 4 and later the "Show PCIe Hard Interface Pins” for the Cyclone® V GX (5CGXFC5C6U19A7) incorrectly shows PIN R16 (nPERSTL0)as being associated with the PCIe® Hard IP located in the bottom transceiver bank.

    Resolution

    The correct pin location for the Hard IP located in the bottom transceiver bank is PIN R17 (nPERSTL1)

    This problem is currently scheduled to be fixed in a future version of the Quartus II software

    Related Products

    This article applies to 1 products

    Cyclone® V GX FPGA

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