Description
You may see the above error in the Arria® 10 device Transceiver CMU PLL IP Parameter Editor Message Pane when using Quartus® Prime version 15.1.2 and later.
This occurs when configuring for an output serial clock frequency of 1485MHz for SDI applications running at a datarate of 2970Mbps.
The CMU PLL minimum VCO specification was updated to 2.45GHz in Quartus version 15.1.2.
Resolution
To implement an SDI datarate of 2970Mbps you must change the CMU PLL output frequency to 2970MHz and activate a local divider in the Transceiver Native PHY IP.