For most FIFO buffers, FLEX 10K embedded array blocks (EABs) provide high performance and large RAM blocks without a logic/memory tradeoff. Because Altera devices are cost-effective, a FIFO buffer made up of logic elements (LEs) only can also provide a competitive solution.
When using FIFO buffers, you should consider various system requirements. For example, you must consider whether a FIFO buffer needs to be read and written simultaneously. Some FIFO buffers require separate read and write clocks while others use the same clock for reading and writing. Altera offers FIFO solutions to meet all of these requirements.
This article discusses the following FIFO designs:
- Interleaved-memory FIFO buffer
- Cycle-shared FIFO buffer
- Synchronous LE-based FIFO buffer
- Asynchronous LE-based FIFO buffer
Interleaved-Memory FIFO Buffer
The interleaved-memory FIFO buffer is suited for relatively deep buffers that have one read/write clock. For this type of FIFO buffer, two EABs are used for each 8 bits of width. You can implement a FIFO buffer up to 512 words deep without using additional EABs.
Each EAB can be read or written on a given clock cycle. By using two EABs, you can implement simultaneous reads and writes. Data is pre-fetched from the non-written EAB, which prevents conflicts that would otherwise occur if a simultaneous read and write to the same EAB were required. This FIFO buffer can achieve 80-MHz performance in FLEX 10KA devices.
Cycle-Shared FIFO Buffer
The cycle-shared FIFO buffer is suited for designs that use many EABs, because it uses fewer EABs than the interleaved-memory FIFO buffer. This FIFO buffer has one read/write clock, and its EABs are time-domain multiplexed with a doubled clock. That is, an EAB is read and written on subsequent doubled clock cycles. Using a 66-MHz clock, you can implement a cycle-shared FIFO buffer with 33-MHz throughput. This FIFO buffer can achieve 40-MHz performance in FLEX 10KA devices.
Arbitrated FIFO Buffer
In some FIFO applications, simultaneous reading and writing is not required. For example, an asynchronous transfer mode (ATM) design may have FIFO buffers where an entire 53-byte cell is read or written in one burst. The ATM design may have multiple FIFO buffers with one port writing a cell to one FIFO buffer while another port reads a cell from a different FIFO buffer. In this case, simultaneous reading and writing is not required. An application that does not require simultaneous reads and writes can use an arbitrated FIFO buffer, which uses an EAB to store the data. Because the arbitrated FIFO does not require simultaneous reads and writes, special techniques are not required to use the EAB. You can use a parameter to prioritize reading or writing. The arbitrated FIFO buffer uses one read/write clock, running over 80 MHz in FLEX 10KA devices.
Synchronous LE-Based FIFO Buffer
Sometimes more FIFO buffers are required than can fit into the EABs of a target device. Alternatively, a FIFO buffer may be required in a design that is targeted for a device without EABs (e.g., FLEX 6000 devices). In this case, a synchronous LE-based FIFO buffer, which uses shift registers to store data in the FIFO buffer, provides a cost-effective solution. This FIFO buffer is ideal for multiple shallow, wide FIFO buffers with one read/write clock. The synchronous LE-based FIFO buffer is best used in high-speed applications, and can achieve over 100-MHz performance.
Asynchronous LE-Based FIFO Buffer
For applications that require distinct read and write clocks, the asynchronous LE-based FIFO buffer offers an ideal solution. For example, a FIFO buffer may buffer data coming from a 33-MHz PCI bus to a 50-MHz back end. These FIFO buffers are referred to as "asynchronous," "two-clock," or "bisynchronous." The asynchronous LE-based FIFO buffer uses a bank of registers to store data. The write counter is decoded to determine which registers are written and a multiplexer is used to determine which registers are read.
A memory structure created from registers and multiplexers can be read and written simultaneously, because the reading multiplexer is independent of the write decoders. This structure can be written and read with different clocks. The FIFO buffer control circuitry prevents any metastable disturbances in the system.
The asynchronous LE-based FIFO buffer is ideal for applications with independent read and write clocks, and it can be combined with other FIFO buffers to create larger FIFO buffers with independent read and write clocks. It can achieve 60-MHz performance in FLEX 10KA devices.
MAX PLUS II Support
You can obtain the design files for the FIFO buffers mentioned in this article from Altera Applications. The FIFO buffers are parameterizable, which makes it easy to set the parameters for your system requirements and customize the function for your design. Additionally, FIFO buffers are provided with Altera's MAX PLUS® II software (such as the cycle-shared FIFO buffer, csfifo). Altera plans to provide additional functions with future versions of the MAX PLUS II software.
Conclusion
FLEX devices provide excellent solutions for designs with FIFO requirements. These solutions meet a wide variety of FIFO requirements and offer high performance and large size at low cost. If you have a design with FIFO requirements, contact your local field applications engineer for more information.