Article ID: 000081217 Content Type: Troubleshooting Last Reviewed: 12/15/2015

Hard IP for PCI Express User Guides Shows Incorrect Value for Receiver Detect Capacitor

Environment

  • Quartus® II Subscription Edition
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT

    Critical Issue

    Description

    The Debugging chapter of the 12.01 versions of the Stratix V Hard IP for PCI Express User Guide, Arria V Hard IP for PCI Express User Guide , and Cyclone V Hard IP for PCI Express User Guide states that the receiver detect circuitry must have a 100 uF capacitor on the TX pins. The correct value for the TX capacitors is 0.1 uF.

    Resolution

    This issue is fixed in the December, 2012 veresions of the Stratix V Hard IP for PCI Express User Guide, Arria V Hard IP for PCI Express User Guide , and Cyclone V Hard IP for PCI Express User Guide

    Related Products

    This article applies to 1 products

    Stratix® V FPGAs

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