Article ID: 000081170 Content Type: Troubleshooting Last Reviewed: 11/11/2011

rst_rxd Warning for Interlaken MegaCore Function 10- and 20-Lane Variations With Transceivers

Environment

Quartus Edition

Quartus® II Subscription Edition

Version Found: 10.1 Version Fixed: 11.1

FPGA Intellectual Property

Interlaken

Version Found: 10.1 Version Fixed: 11.1

BUILT IN - ARTICLE INTRO SECOND COMPONENT

Critical Issue

Description

When you compile an Interlaken MegaCore function 10- or 20-lane variation with transceivers, the following warning message appears:

Warning: Verilog HDL or VHDL warning at alt_ntrlkn_hsio_bank_pmad5.v(92): object “rst_rxd” assigned a value but never read

Resolution

This issue has no workaround. However, this issue has no design impact. You can ignore this warning message.

This issue is fixed in version 11.1 of the Interlaken MegaCore function.

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