Article ID: 000081166 Content Type: Troubleshooting Last Reviewed: 09/11/2012

Do I need to synchronize my FIFO aclr signal to my rdclk or wrclk signals?

Environment

BUILT IN - ARTICLE INTRO SECOND COMPONENT
Description

For Stratix®, Cyclone® and earlier families, there is no read clock (rdclk) sensitivity on aclr. For Stratix II, Cyclone II, and newer device families, the rdclk sensitivity on aclr is removed beginning with the Quartus® II software version 5.1.  The dcfifo megafunction automatically inserts an internal rdclk / aclr synchronization register for these devices, beginning with version 5.1. 

However, the megafunction does not automatically insert an internal write clock (wrclk) synchronization register for aclr, because doing so may affect latency depending on aclr timing. The Single & Dual-Clock FIFO Megafunctions User Guide (PDF) explains how you can manually add a synchronization register between aclr and wrclk.

Related Products

This article applies to 2 products

Cyclone® II FPGA
Stratix® II FPGAs

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