Article ID: 000081156 Content Type: Troubleshooting Last Reviewed: 08/10/2015

BARs must be disabled when using Root Port

Environment

    Quartus® II Subscription Edition
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Description

You will see this message if you have enabled Base Address Registers (BARs) for the Avalon Memory-Mapped (Avalon-MM) of the Altera® Hard IP core for PCI Express® with Port type set to Native Endpoint, but then switch to Port type Root Port.

For example:

1)  Enable BAR0 (32-bit non prefetchable)
2)  Enable BAR1 (32-bit non prefetchable)
3)  Change the Port Type from Native endpoint to Root port

Resolution

To work around this issue:

Re-select the Endpoint type, disable all BARs, then re-select Root Port type.

This behavior is not scheduled to be changed in a future Quartus® II software version.

Related Products

This article applies to 17 products

Arria® V GX FPGA
Intel® Arria® 10 GX FPGA
Cyclone® V GT FPGA
Arria® V GT FPGA
Intel® Arria® 10 SX SoC FPGA
Arria® V GZ FPGA
Intel® Arria® 10 GT FPGA
Cyclone® V GX FPGA
Arria® V ST SoC FPGA
Arria® V SX SoC FPGA
Cyclone® V SE SoC FPGA
Cyclone® V ST SoC FPGA
Cyclone® V SX SoC FPGA
Stratix® V E FPGA
Stratix® V GS FPGA
Stratix® V GT FPGA
Stratix® V GX FPGA

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