Article ID: 000081112 Content Type: Troubleshooting Last Reviewed: 08/29/2012

Why is the value of the DQS delay chains incorrect in timing simulation when DQS phase shift is used?

Environment

BUILT IN - ARTICLE INTRO SECOND COMPONENT
Description

The standard delay output files (.sdo) generated by the EDA Netlist Writer in the Quartus® II software version 9.0 contain incorrect delay values for DQS delay chains. Therefore any specified DQS phase shift is not reflected correctly during simulation.

To work around the problem, in the generated .sdo file, manually change the IOPATH delay of the "<device>_dqs_delay_chain" atom into a PORT delay. 

For example:

The following code shows a portion of an original .sdo file, with an  IOPATH delay:


(CELL
  (CELLTYPE "stratixiii_dqs_delay_chain")
  (INSTANCE dqdqs\|dqs_delay_chain_inst)
  (DELAY
     (ABSOLUTE
           (IOPATH dqsin dqsbusout (612:612:612)  (571:571:571))
       )
    )
)


Change the IOPATH delay, to a PORT delay. Do not change the delay values (in this example (612:612:612 and 571:571:571)):

(CELL
  (CELLTYPE "stratixiii_dqs_delay_chain")
  (INSTANCE dqdqs\|dqs_delay_chain_inst)
  (DELAY
     (ABSOLUTE
       (PORT dqsin (612:612:612)  (571:571:571))   
       )
    )
)

This problem is scheduled to be fixed in a future version of the Quartus II software.

Related Products

This article applies to 2 products

Stratix® III FPGAs
Arria® II GX FPGA

Disclaimer

1

All postings and use of the content on this site are subject to Intel.com Terms of Use.