Article ID: 000081111 Content Type: Product Information & Documentation Last Reviewed: 01/01/2015

How do I fix the link down training hardware issues in my PCI Express HIP Gen2 x4 or x8 design in Stratix IV GX/GT devices in Quartus 9.1 SP1 software?

Environment

  • Reset
  • PCI Express
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

     

    If you are experiencing problems with link training or down training in Stratix® IV devices using the PCI Express Compiler targeting the hardware IP block (HIP) in gen2 x4 or x8 in Quartus® II software version 9.1sp1, please install patch 1.19. This patch uses Rx signal detect logic in the physical media attachment (PMA) to hold the physical coding sublayer (PCS) rx_digitalreset signal in reset until the Rx serial interface is locked.

    This patch replaces the 3 ms circuit employed by the Design Example in Chapter 7 of the PCI Express Compiler User Guide (PDF).

    After installing this patch, you will need to regenerate your PCI Express core. Note that your application logic does not require any change as the regenerated variant port signature remains unchanged.

    Download the Quartus II software version 9.1 SP1 patch 1.19 for PC:

    - Patch: PC-Quartus_II-9_1_SP1-1_19.exe

    - Readme: PC-Quartus_II-9_1_SP1-1_19-README

    Download the Quartus II software version 9.1 SP1 patch 1.19 for Linux:

    - Patch: Linux-Quartus_II-9.1_SP1-1.19.tar

    - Readme: Linux-Quartus_II-9.1_SP1-1.19-README

     

    Related Products

    This article applies to 1 products

    Stratix® IV GX FPGA

    Disclaimer

    1

    All postings and use of the content on this site are subject to Intel.com Terms of Use.