Article ID: 000081110 Content Type: Troubleshooting Last Reviewed: 09/11/2012

Why does my initialized RAM block memory content get overwritten even though the WREN signal is connected to GND permanently?

Environment

BUILT IN - ARTICLE INTRO SECOND COMPONENT
Description

There is an issue in the Quartus® II software version 5.0 that can cause a small percentage of designs that use the ALTSYNCRAM megafunction to generate incorrect logic.

This issue has been fixed beginning with the Quartus II software version 5.0 service pack 1. To download the service pack, go to the 5.0 Service Pack 1 download page.

When this issue occurs, the RAM design will not act like a ROM even though you connected the write enable signal to GND. The initial data specified in a Memory Initialization File (.mif) or Hexadecimal (Intel-Format) File (.hex) file will get unintentionally overwritten. Simulations do not display this problem. Note that this issue does not occur if you compiled your design with the Quartus II software versions 4.2 or earlier.

Related Products

This article applies to 1 products

Stratix® II FPGAs

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