Yes it is possible to use the SignalTap® II Logic Analyzer in Stratix® V, Arria® V or Cyclone® V series devices which have the design security key programmed and the tamper-protection bit set.
Enabling the tamper-protection bit places the device in JTAG secure mode upon power up. During JTAG secure mode, many JTAG instructions are disabled which would prevent the usage of SignalTap. However issuing the UNLOCK JTAG instruction can deactivate this mode, allowing SignalTap to be used. This instruction can only be executed via the core.
In order to use SignalTap with these devices, please follow the steps below.
Firstly note that you will need two different designs, one which issues the UNLOCK JTAG command as described in AN556: Using the Design Security Features in Altera FPGAs (PDF) , and another design which instantiates SignalTap.
Note also that since configuration over JTAG is disabled when the tamper-protection bit is enabled, the device will need to be configured using an encrypted bit stream for both of these designs over Passive Serial (PS), Active Serial (AS) or Fast Passive Parallel (FPP) configuration modes.
1. Configure the device with the encrypted design which issues the UNLOCK JTAG command via the core.
2. Do not power cycle the device after issuing the UNLOCK JTAG command.
3. Reconfigure the device with the encrypted design which has the SignalTap instance.
4. Use SignalTap as normal.
5. In order to bring the device back to LOCK state, simply power cycle the device.