Article ID: 000081089 Content Type: Troubleshooting Last Reviewed: 09/11/2012

Where are the VCCIO pins located for PLL banks 9, 10, 11 and 12 as noted in the Stratix pin-out files on the web?

Environment

BUILT IN - ARTICLE INTRO SECOND COMPONENT
Description The VCC_PLL pins power the output buffers of the pins located in banks 9, 10, 11 and 12 and should be connected to the VCCIO voltage of the selected I/O standard. VCC_PLL5_OUTA = VCCIO for Bank 9 VCC_PLL5_OUTB = VCCIO for Bank 10 VCC_PLL6_OUTA = VCCIO for Bank 11 VCC_PLL6_OUTB = VCCIO for Bank 12

Related Products

This article applies to 1 products

Stratix® FPGAs

Disclaimer

1

All postings and use of the content on this site are subject to Intel.com Terms of Use.